The electronics industry has been progressing with the miniaturization of electronic devices. This trend influences semiconductor packaging technology, which enables the connection between bare IC chips and other components, and enables the connection between bare IC chips and other components. Typically, a semiconductor package has a footprint much larger than that of the chip. To adapt to the miniaturization trend, the size difference between the package and the chip has been reduced, producing a new package type called a Chip scale package (CSP). A chip scale package is loosely defined as a package that takes no more than about 20% additional area (length and width) than the bare silicon die. The solder balls of chip scale packages are smaller than ball grid array (BGA) that had arranged according to international standard of Joint Electron Device Engineering Council (JEDEC). When it comes to personal and portable electronic devices, smaller is better, and various products need different chip scale package types, a wide array of which are currently available.
Certain semiconductor devices are designed to handle relatively high voltages in a compact space. For example, semiconductor devices that are exposed to RMS voltages greater than 100 VAC, such as 265 VAC or 415 VAC, are often mounted in electronic power supplies and the like. These devices may dissipate relatively large amounts of power, and are accordingly often mounted to heat sinks or like devices as well as being electrically connected to electronic equipment of various types.
Many such semiconductor devices for power applications are commonly available in the JEDEC standard TO-220 and DO-218 packages (www.jedec.org). An illustrative TO-220 package 110 is shown in FIG. 1. The TO-220 package 110 includes a pressure clamp 140, retainer 130, heat sink 120, a spacer 150 interposed between the package 110 and the heat sink 120, and a semiconductor die (not visible in FIG. 1) with leads 114 exiting the package 110 on one side. High-voltage semiconductor devices may also be available in various other packages similar to the TO-220 package.
The continued emphasis on faster, smaller, lighter, and lower cost electronics systems is making component, board and system packaging more complex each year. The increase in complexity is due to wider use of finer pitch and thinner array surface mount packages, which are the key to miniaturization of electronics products. Most of the components on a typical systems motherboard for desk top computer systems remain at 1.27 and 1.00 mm pitch surface mount components with increasing use of finer pitch (0.80, 0.65, 0.50 & 0.40 mm) array styled packages. Portable systems are moving to the finer pitches at a faster rate. The component pitch and overall profile height plays a critical role in the complexity of manufacturing process. The use of finer pitch, low profile components demands assembly equipment and processes that operate with tighter specification limits. The assembly processes that demand a higher precision include: pick-and-place, solder paste-printing applications, reflow, inspection, and rework. The use of finer pitch low profile components increases the complexity, which could negatively effect yield and rework making assemblies more difficult and costly.
One aspect of the packaging process that can reduce yield is the accuracy with which the semiconductor die can be mounted to the heat sink or slug. The accuracy of this process relies primarily on the pick and place machine that is employed. In addition, another packaging aspect of the packaging process that can also reduce yield is the accuracy with which the solder thickness can be controlled.